Advent of FPGA — A Jane Street Challenge

For years, Advent of Code has been a cherished end-of-year tradition at Jane Street, attracting many employees eager to engage in a month-long series of programming puzzles. These challenges are designed to encourage deep thinking, innovative problem-solving, and thoughtful engineering—qualities that align perfectly with the company’s culture. Building on this tradition, last year, Anish, a hardware engineer at Jane Street, took a novel approach by implementing the entire Advent of Code series using Hardcaml, an OCaml-based hardware description language (HDL). This effort not only transformed software algorithms into synthesizable FPGA circuits but also provided a unique opportunity to explore architectural design and resource optimization within hardware constraints. His detailed account, titled Advent of Hardcaml, walks readers through the intricacies of translating puzzles into hardware, showcasing the creative potential in this domain. This year, Jane Street is excited to expand this initiative by launching the 2025 Advent of FPGA Challenge. The challenge invites the community to build synthesizable register-transfer level (RTL) designs that solve selected Advent of Code 2025 puzzles. Participants may choose as many puzzles as they wish, with a minimum of one, and are encouraged to use Hardcaml for bonus recognition. The challenge emphasizes realistic resource usage and requires designs to be synthesizable, although actual FPGA implementation is not mandatory. Submissions must include open-source code, a testbench, and documentation explaining the approach and execution steps. Importantly, all work must be original—duplicates or AI-generated submissions are disallowed—and participants should be able to clearly describe their designs. The competition welcomes RTL written in any language, including Verilog, VHDL, Chisel, Amaranth, and Filament, with Hardcaml particularly encouraged. However, high-level synthesis (HLS) languages are excluded. To support participants, Jane Street provides resources such as a Hardcaml template/demo project, setup instructions, and various tutorials with examples. The submission deadline is January 16, 2026, and solutions are to be submitted through a designated form. The challenge will recognize the three most inventive and creative contributions, chosen by the Jane Street hardware team, with prizes including FPGA development kits—the Zynq UltraScale+ Kria KV260—and Jane Street swag. Additionally, anyone who completes at least one puzzle using Hardcaml will receive a Jane Street Hardcaml T-shirt. To inspire participants, Jane Street suggests areas for exploration such as scalability (handling inputs 10 to 1000 times larger), efficiency (balancing area and performance trade-offs), architecture (leveraging FPGA-native parallelism and pipelining), physical synthesis using open-source ASIC flows like TinyTapeout, and language-specific features that enable elegant hardware designs beyond traditional Verilog and VHDL. Jane Street hopes this challenge will foster creativity and encourage wider adoption of Hardcaml across academic and open-source communities. Participants are invited to reach out with questions or submission issues via advent-of-fpga@janestreet.com. Ben, a hardware developer at Jane Street originally from New Zealand with a Ph.D. in electrical engineering from the University of Tokyo, and Anish, an FPGA engineer who joined Jane Street in 2024 from Carnegie Mellon, are among the team members supporting this initiative. Both share interests in advancing hardware design through innovative tools and community engagement, making this challenge a perfect blend of technical rigor and collaborative enthusiasm.